The present invention relates to delay compensation, and more particularly, this invention relates to delay compensation in global phase-locked loop- or phase lock loop-(PLL)-based timing recovery loops.
A PLL is a control system that generates a signal that has a fixed relation to the phase of a “reference” signal. A PLL circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase.
Analog PLLs generally include a phase detector, low pass filter and voltage-controlled oscillator (VCO) placed in a negative feedback closed-loop configuration. There may be a frequency divider in the feedback path or in the reference path, or both, in order to make the PLL's output signal frequency an integer multiple of the reference. A non integer multiple of the reference frequency can be created by replacing the simple divide-by-N counter in the feedback path with a programmable pulse swallowing counter. This technique is usually referred to as a fractional-N synthesizer or fractional-N PLL.
The oscillator generates a periodic output signal. Assume that initially the oscillator is at nearly the same frequency as the reference signal. Then, if the phase from the oscillator falls behind that of the reference, the phase detector changes the control voltage of the oscillator, so that it speeds up. Likewise, if the phase creeps ahead of the reference, the phase detector changes the control voltage to slow down the oscillator. A low-pass filter smooths out abrupt changes in the control voltage; it can be demonstrated that some filtering is required for a stable system. Since initially the oscillator may be far from the reference frequency, practical phase detectors may also respond to frequency differences, so as to increase the lock-in range of allowable inputs.
Depending on the application, either the output of the controlled oscillator, or the control signal to the oscillator, provides the useful output of the PLL system.
A Digital Phase-Locked Loop (DPLL) operates similarly to an analog phase-locked loop, but is implemented entirely using digital circuits. In place of a voltage-controlled oscillator (VCO), a DPLL uses a counter with a variable divisor. DPLLs are sometimes used for data recovery.
Loop delay in timing control loops is known to degrade system performance. In any PLL implementation, therefore, the designer aims at minimizing loop delay, so that the PLL phase margin is maximized and a stiff and robust behavior of the timing control loop is achieved. Unfortunately, implementation and architectural constraints often introduce some substantial delay in the timing loop circuit. Such unavoidable loop delays then force the designer to re-adjust the PLL phase margin and bandwidth, and thereby suffer a loss in PLL performance. In data storage applications, the reduced PLL performance translates into a performance loss of the overall read channel. Consequently, the raw bit-error rate of the read channel is degraded.
As another example, a well-known trade-off situation arises when the data decisions needed to drive the timing control loop are taken from a sequence detector rather than from a slicer. The motivation for using decisions from the sequence detector is that these decisions are more reliable than the slicer decisions. However, decisions from the sequence detector can only be generated with some inherent delay. Hence, the advantage of using more reliable decisions is partly lost due to the fact that additional decision delay is now involved.
To combat these problems, an attractive approach consists of compensating for the delay in the timing control loop. This can be achieved by introducing a prediction element into the design of the PLL. However, such approaches assume a specific model for the evolution of the signal frequency. More precisely, the frequency offset is assumed to be constant in the absence of noise. The drawback of this assumption is that the tracking capability of the delay compensation circuit is limited in case the actual frequency does not follow this model. It is for example well known that rapid variations in the frequency offset are often experienced in tape systems. Moreover, such systems have been limited to single channel applications.